In recent years, an increasing number of information terminals such as mobile phone and personal computer has become equipped with nonvolatile memories such as flash memory, and accordingly development of microcomputers and SoC (System on Chip) equipped with nonvolatile memories has advanced.
Such a nonvolatile memory, particularly flash memory, requires a high voltage to be generated when memory data is to be rewritten, and is thus mounted with an internal register in which information about a high voltage level at the time of rewriting is set. In addition, it is mounted with an address latch circuit in which information about a memory address of a memory cell to be rewritten is stored and, depending on this information, a word line of the memory cell to be rewritten is selected.
If momentary power interruption or the like occurs at the time when memory data of the flash memory is to be rewritten, the information about the high voltage level stored in the internal register and/or the information about the memory address stored in the address latch circuit may be broken.
At this time, if the system cannot detect the momentary power interruption, it cannot know the fact that the high voltage level information and/or the memory address information in the flash memory has been broken, and therefore, generation of an abnormal rewrite voltage, erroneous writing into a memory cell other than the memory cell to be rewritten, or the like, may cause the memory data to be broken. As technologies relevant to this, inventions are disclosed in Patent Documents PTDs 1 to 2 referenced below.
PTD 1 aims to provide a microcomputer capable of recovering a high-speed operation in a short time even if momentary power interruption occurs during the high speed operation. After powered up, the microcomputer examines a value of a comparison register. If the comparison register is not set to a specified value, the specified value is set in the comparison register, and selection data for selecting a ceramic oscillator is simultaneously set in an oscillation selection register and an auxiliary register. In contrast, if momentary power interruption occurs while the comparison register is set to the specified value, the value of the auxiliary register is set in the oscillation selection register 13.
PTD 2 has the following problem to be solved. In the case where a main memory is entirely constituted of nonvolatile memories and sudden power shutoff occurs, the system cannot normally resume its operation when re-powered up. The device includes an abnormal power shutoff determination unit and an abnormal power termination notification register. When the device is powered up, the abnormal power shutoff determination unit refers to the abnormal power termination notification register. When the abnormal power termination notification register stores information which indicates that the power supply for the device has abnormally been shut off and the processor is not a nonvolatile processor, the determination unit restarts the process which was executed before the shutoff of the power supply for the device and examines a device driver. When the abnormal power termination notification register stores information which indicates that the power supply for the device has abnormally been shut off and the processor is a nonvolatile processor, the determination unit restarts the process which was executed before the shutoff of the power supply for the device, from interrupted processing, and examines the device driver.